PIC16F7X7 datasheet(186/276 Pages) MICROCHIP

186 / 276 page

PIC16F7X7

DS30498C-page 184

 2004 Microchip Technology Inc.

15.15 Interrupts

The PIC16F7X7 has up to 17 sources of interrupt. The

Interrupt Control register (INTCON) records individual

interrupt requests in flag bits. It also has individual and

global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector

immediately. Individual

interrupts

can

disabled through their corresponding enable bits in

various registers. Individual interrupt bits are set

regardless of the status of the GIE bit. The GIE bit is

cleared on Reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the

Special Function Register, PIR1. The corresponding

interrupt enable bits are contained in Special Function

contained in Special Function Register, INTCON.

When an interrupt is serviced, the GIE bit is cleared to

disable any further interrupt, the return address is

pushed onto the stack and the PC is loaded with 0004h.

Once in the Interrupt Service Routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software

before

re-enabling

interrupts

avoid

recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends on when the interrupt event occurs relative to

the current Q cycle. The latency is the same for one or

two-cycle instructions. Individual interrupt flag bits are

set regardless of the status of their corresponding

mask bit, PEIE bit or the GIE bit.

FIGURE 15-11:

INTERRUPT LOGIC

Note:

Individual interrupt flag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

OSFIF

OSFIE

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

TMR0IF

TMR0IE

INT0IF

INT0IE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

PSPIF(1)

PSPIE(1)

CCP1IF

CCP1IE

CMIE

CMIF

BCLIF

BCLIE

CCP3IF

CCP3IE

CCP2IF

CCP2IE

Note 1:

PSP interrupt is implemented only on PIC16F747/777 devices.

PIC16F7X7 Datasheet(PDF) 186 Page - Microchip Technology

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