PIC16F7X7 datasheet(190/276 Pages) MICROCHIP

190 / 276 page

PIC16F7X7

DS30498C-page 188

 2004 Microchip Technology Inc.

15.17.3

TWO-SPEED CLOCK

START-UP MODE

Two-Speed Start-up minimizes the latency between

oscillator start-up and code execution that may be

selected with the IESO (Internal/External Switchover)

bit in Configuration Word Register 2. This mode is

achieved by initially using the INTRC for code

execution until the primary oscillator is stable.

If this mode is enabled and any of the following condi-

tions exist, the system will begin execution with the

INTRC oscillator. This results in almost immediate

code execution with a minimum of delay.

• POR and after the Power-up Timer has expired (if

PWRTEN = 0)

• or following a wake-up from Sleep

• or a Reset, when running from T1OSC or INTRC

(after a Reset, SCS<1:0> are always set to ‘00’).

If the primary oscillator is configured to be anything

other than XT, LP or HS, then Two-Speed Start-up is

disabled because the primary oscillator will not require

any time to become stable after POR or an exit from

Sleep.

If the IRCF bits of the OSCCON register are configured

to a non-zero value prior to entering Sleep mode, the

secondary system clock frequency will come from the

output of the INTOSC. The IOFS bit in the OSCCON

will allow the user to determine when the internal

oscillator can be used for time critical applications.

Checking the state of the OSTS bit will confirm

whether the primary clock configuration is engaged. If

not, the OSTS bit will remain clear.

When the device is auto-configured in INTRC mode

following a POR or wake-up from Sleep, the rules for

entering other oscillator modes still apply, meaning the

SCS<1:0> bits in OSCCON can be modified before the

OST time-out has occurred. This would allow the

application to wake-up from Sleep, perform a few

instructions using the INTRC as the clock source and

go back to Sleep without waiting for the primary

oscillator to become stable.

15.17.3.1

Two-Speed Start-up Sequence

Wake-up from Sleep, Reset or POR.

OSCON bits configured to run from INTRC

(31.25 kHz).

Instructions

begin

execution

INTRC

(31.25 kHz).

OST enabled to count 1024 clock cycles.

OST timed out, wait for falling edge of INTRC.

OSTS is set.

System clock held low for eight falling edges of

new clock (LP, XT or HS).

System clock is switched to primary source (LP,

XT or HS).

The software may read the OSTS bit to determine

when the switchover takes place so that any software

timing edges can be adjusted.

FIGURE 15-13:

TWO-SPEED START-UP

Note:

Following any Reset, the IRCF bits are

zeroed and the frequency selection is

forced to 31.25 kHz. The user can modify

the IRCF bits to select a higher internal

oscillator frequency.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit to remain clear.

Q3 Q4

Q1 Q2

OSC1

Sleep

Program

0000h

INTRC

TOST

Q3 Q4

OSC2

OSTS

System Clock

0001h

Q1 Q2 Q3 Q4 Q1 Q2

Counter

0004h

0005h

0003h

Q1 Q2 Q3 Q4

CPU Start-up

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