PIC24FJ256DA206 datasheet(25/408 Pages) MICROCHIP

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DS39969B-page 25

PIC24FJ256DA210 FAMILY

PGEC1

I/O

In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1.

PGED1

I/O

In-Circuit Debugger/Emulator/ICSP Programming Data 1.

PGEC2

I/O

In-Circuit Debugger/Emulator/ICSP Programming Clock 2.

PGED2

I/O

In-Circuit Debugger/Emulator/ICSP Programming Data 2.

PGEC3

I/O

In-Circuit Debugger/Emulator/ICSP Programming Clock 3.

PGED3

I/O

In-Circuit Debugger/Emulator/ICSP Programming Data 3.

PMA0

—

I/O

Parallel Master Port Address bit 0 Input (Buffered Slave

modes) and Output (Master modes).

PMA1

—

I/O

Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2

—

Parallel Master Port Address bits<22:2>.

PMA3

—

12, 60(1)

F2, G11(1)

O—

PMA4

—

11,59(1)

F4,G10(1)

O—

PMA5

—

10,40(1)

E3,K6(1)

O—

PMA6

—

PMA7

—

PMA8

—

L11

—

PMA9

—

L10

—

PMA10

—

PMA11

—

PMA12

—

PMA13

—

PMA14

—

C11

—

PMA15

—

D11

—

PMA16

—

PMA17

—

PMA18

—

40,10(1)

K6,E3(1)

O—

PMA19

—

PMA20

—

59, 11(1)

G10, F4(1)

O—

PMA21

—

60,12(1)

G11,F2(1)

O—

PMA22

—

66,9(1)

E11,E1(1)

O—

PMACK1

—

A10

ST/TTL Parallel Master Port Acknowledge Input 1.

PMACK2

—

E10

ST/TTL Parallel Master Port Acknowledge Input 2.

PMALL

—

Parallel Master Port Lower Address Latch Strobe.

PMALH

—

Parallel Master Port Higher Address Latch Strobe.

PMALU

—

Parallel Master Port Upper Address Latch Strobe.

PMBE0

—

Parallel Master Port Byte Enable Strobe 0.

PMBE1

—

Parallel Master Port Byte Enable Strobe 1.

PMCS1

—

71(3),18

C11(3),G1

I/O

ST/TTL Parallel Master Port Chip Select Strobe 1.

PMCS2

—

70(2),9,

66(1)

D11(2),E1,

E11(1)

O—

Parallel Master Port Chip Select Strobe 2.

TABLE 1-3:

PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

Pin Number

I/O

Input

Buffer

Description

64-Pin

TQFP/QFN

100-Pin

TQFP

121-Pin

BGA

Legend:

TTL = TTL input buffer

ST = Schmitt Trigger input buffer

ANA = Analog level input/output

I2C™ = I2C/SMBus input buffer

Note 1:

The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’.

The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.

The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.

The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.

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