PIC24FJ256DA206 datasheet(97/408 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39969B-page 97

PIC24FJ256DA210 FAMILY

The CORCON register contains the IPL3 bit, which,

together with IPL<2:0>, indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The interrupt controller has the Interrupt Controller Test

interrupt controller. When an interrupt request occurs,

it’s associated vector number and the new interrupt pri-

ority level are latched into INTTREG. This information

can be used to determine a specific interrupt source if

a generic ISR is used for multiple vectors (such as

when ISR remapping is used in bootloader applica-

tions) or to check if another interrupt is pending while in

an ISR.

All interrupt registers are described in Register 7-1

through Register 7-40 in the succeeding pages.

SR: ALU STATUS REGISTER (IN CPU)

U-0

R-0, HSC

—

DC(1)

bit 15

bit 8

R/W-0, HSC

R/W-0, HSC R/W-0, HSC

R-0, HSC

R/W-0, HSC R/W-0, HSC

IPL2(2,3)

IPL1(2,3)

IPL0(2,3)

RA(1)

N(1)

OV(1)

Z(1)

C(1)

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented: Read as ‘0’

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111

= CPU interrupt priority level is 7 (15); user interrupts are disabled

110

= CPU interrupt priority level is 6 (14)

101

= CPU interrupt priority level is 5 (13)

100

= CPU interrupt priority level is 4 (12)

011

= CPU interrupt priority level is 3 (11)

010

= CPU interrupt priority level is 2 (10)

001

= CPU interrupt priority level is 1 (9)

000

= CPU interrupt priority level is 0 (8)

Note 1:

See Register 3-1 for the description of the remaining bits (bit 8, 4, 3, 2, 1 and 0) that are not dedicated to

interrupt control functions.

The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.

The value in parentheses indicates the interrupt priority level if IPL3 = 1.

The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

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