SPMC68CK338CPV14 datasheet(24/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-

cle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a sys-

tem contains external bus masters, an external bus monitor must be implemented and the internal to

external bus monitor option must be disabled.

3.4.3 Halt Monitor

The halt monitor responds to assertion of the HALT signal on the internal bus caused by a double bus

fault. A double bus fault occurs when:

• Bus error exception processing begins and a second BERR is detected before the first instruction

of the first exception handler is executed.

• One or more bus errors occur before the first instruction after a reset exception is executed.

• A bus error occurs while the CPU is loading information from a bus error stack frame during a re-

turn from exception (RTE) instruction.

If the halt monitor is enabled by setting HME in SYPCR, the MCU will issue a reset when a double bus

fault occurs, otherwise the MCU will remain halted.

A flag in the reset status register (RSR) indicates that the last reset was caused by the halt monitor.

3.4.4 Spurious Interrupt Monitor

The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt ac-

knowledge cycle. Leaving IARB[3:0] set to %0000 in the module configuration register of any peripheral

that can generate interrupts will cause a spurious interrupt.

3.4.5 Software Watchdog

The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a

service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog

times out and issues a reset. This register can be written at any time, but returns zeros when read.

Each time the service sequence is written, the software watchdog timer restarts. The servicing se-

quence consists of the following steps:

Write $55 to SWSR.

Write $AA to SWSR.

Both writes must occur before time-out in the order listed, but any number of instructions can be exe-

cuted between the two writes.

The watchdog clock rate is affected by SWP and SWT[1:0] in SYPCR. When SWT[1:0] are modified, a

watchdog service sequence must be performed before the new time-out period takes effect.

The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of RESET. Refer

to Table 11.

SWSR — Software Service Register

$YFFA27

NOT USED

SWSR

RESET:

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SPMC68CK338CPV14 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

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