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SPMC68CK338CPV14 Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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SPMC68CK338CPV14 Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 133 page  MOTOROLA MC68CK338 86 MC68CK338TS/D Figure 19 CPSM Block Diagram 6.5.1 CPSM Registers The CPSM contains a control register and a test register. All unused bits and reserved address loca- tions return zero when read by the software. Writing to unused bits and reserved address locations has no effect. PRUN — Prescaler Running The PRUN bit is a read/write control bit that allows the software to switch the prescaler counter on and off. This bit allows the counters in various CTM6 submodules to be synchronized. It is cleared by reset. 0 = Prescaler is held in reset and is not running 1 = Prescaler is running DIV23 — Divide By 2/Divide By 3 The DIV23 bit is a read/write control bit that selects the division ratio of the first prescaler counter. It may be changed by the software at any time and is cleared by reset. 0 = First prescaler stage divides by two 1 = First prescaler stage divides by three PSEL[1:0] — Prescaler Division Ratio Select Field This bit field selects the division ratio of the programmable prescaler output signal (PCLK6). Refer to Table 49. CPCR — CPSM Control Register $YFF408 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PRUN DIV23 PSEL[1:0] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTM CPSM BLOCK fsys 8-BIT PCLK2 = PCLK3 = PCLK4 = PCLK5 = PCLK6 = FIRST CPSM SELECT PCLK1 = ÷2 ÷4 ÷8 ÷16 ÷32 PRESCALER ÷64 ÷128 ÷256 PRUN DIV23 PSEL1 PSEL0 CPCR PRESCALER ÷2 or ÷3 fsys ÷ 2 fsys ÷ 4 fsys ÷ 8 fsys ÷ 16 fsys ÷ 32 fsys ÷ 64 fsys ÷ 128 fsys ÷ 256 fsys ÷ 512 fsys ÷ 3 fsys ÷ 6 fsys ÷ 12 fsys ÷ 24 fsys ÷ 48 fsys ÷ 96 fsys ÷ 192 fsys ÷ 384 fsys ÷ 768 DIV23 = ÷ 3 DIV23 = ÷ 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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