SPMC68CK338CPV14 datasheet(29/133 Pages) FREESCALE

29 / 133 page

MC68CK338

MOTOROLA

MC68CK338TS/D

The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-

ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-

nated as shown in Figure 10. OP0 is the most significant byte of a long-word operand, and OP3 is the

least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The

single byte of a byte-length operand is OP0.

Figure 10 Operand Byte Order

3.5.9 Operand Alignment

The data multiplexer establishes the necessary connections for different combinations of address and

data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-

sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the

remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-

ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.

ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1]

indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the

byte offset from the base.

3.5.10 Misaligned Operands

CPU32L processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it

overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-

dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address

is on a byte boundary only.

A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address.

The CPU32L does not support misaligned operand transfers, and gives an address error exception if

one is attempted.

The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU

transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the

first bus cycle and the least significant operand word on a following bus cycle.

3.5.11 Operand Transfer Cases

Table 16 summarizes how operands are aligned for various types of transfers. OPn entries are portions

of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and

ADDR0 for that bus cycle.

OP0

OPERAND BYTE ORDER

OP1

OP2

OP3

16 15

8 7

BYTE ORDER

OPERAND

LONG WORD

THREE BYTE

WORD

BYTE

OP2

OP1

OP0

OP1

OP0

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMC68CK338CPV14 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

SPMC68CK338CPV14 Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL