SPMC68CK338CPV14 datasheet(44/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

If an internal source asserts the reset signal, the reset control logic asserts RESET for a minimum of

512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to

assert RESET until the internal reset signal is negated.

After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy-

cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,

reset exception processing begins. If, however, the reset input is at logic level zero, the reset control

logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-

impedance state for ten cycles, then it is tested again. The process repeats until RESET is released.

3.8.5 Power-On Reset

When the SIML clock synthesizer is used to generate the system clock, power-on reset involves special

circumstances related to application of system and clock synthesizer power. Regardless of clock

source, voltage must be applied to clock synthesizer power input pin VDDSYN in order for the MCU to

operate. The following discussion assumes that VDDSYN is applied before and during reset. This mini-

mizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific

crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.

During power-on reset, an internal circuit in the SIML drives the IMB and external reset lines. The circuit

releases the internal reset line as VDD ramps up to the minimum specified value, and SIML pins are

initialized. As VDD reaches a specified minimum value, the clock synthesizer VCO begins operation and

clock frequency ramps up to specified limp mode frequency. The external RESET line remains asserted

until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.

The SIML clock synthesizer provides clock signals to the other MCU modules. After the clock is running

and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and

VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15

milliseconds. During this period, module port pins may be in an indeterminate state. While input-only

pins can be put in a known state by means of external pull-up resistors, external logic on input/output

or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-

ers or isolation resistors to prevent conflict.

3.8.6 Use of Three-State Control Pin

Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,

high-impedance state. The signal must remain asserted for ten clock cycles in order for drivers to

change state. There are certain constraints on use of TSC during power-on reset:

• When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-

up time affects how long the ten cycles take. Worst case is approximately 20 ms from TSC asser-

tion.

• When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-

ance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.

• When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent

mode selection. Once the output drivers change state, the MCU must be powered down and re-

started before normal operation can resume.

3.9 Interrupts

Interrupt recognition and servicing involve complex interaction between the CPU32L, the SIML, and a

device or module requesting interrupt service.

Freescale Semiconductor, Inc.

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SPMC68CK338CPV14 Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc

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