SPMC68CK338CPV14 datasheet(42/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

Data lines have weak internal pull-up drivers. External bus loading can overcome the weak internal pull-

up drivers on data bus lines, and hold pins low during reset. Use an active device to hold data bus lines

low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent

conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is

released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven

lines may be required.

3.8.2 Reset States of SIML Pins

Generally, while RESET is asserted, SIML pins either go to an inactive high-impedance state or are

driven to their inactive states. After RESET is released, mode selection occurs and reset exception pro-

cessing begins. Pins configured as inputs must be driven to the desired active state. Pull-up or pull-

down circuitry may be necessary. Pins configured as outputs begin to function after RESET is released.

Table 32 is a summary of SIML pin states during reset.

Table 31 Reset Mode Selection

Mode Select Pin

Default Function

(Pin Left High)

Alternate Function

(Pin Pulled Low)

DATA0

CSBOOT 16-Bit

CSBOOT 8-Bit

DATA1

CS0

CS1

CS2

BGACK

DATA2

CS3

CS4

CS5

FC0

FC1

FC2

DATA3

DATA4

DATA5

DATA6

DATA7

CS6

CS[7:6]

CS[8:6]

CS[9:6]

CS[10:6]

ADDR19

ADDR[20:19]

ADDR[21:19]

ADDR[22:19]

ADDR[23:19]

DATA8

DSACK[1:0]

AVEC, DS, AS

SIZ[1:0]

PORTE

DATA9

IRQ[7:1]

MODCLK

PORTF

DATA11

Test Mode Disabled

Test Mode Enabled

MODCLK

VCO = System Clock

EXTAL = System Clock

BKPT

Background Mode Disabled

Background Mode Enabled

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