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SPMC68CK338CPV14 Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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SPMC68CK338CPV14 Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 133 page ![]() MC68CK338 MOTOROLA MC68CK338TS/D 33 The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are initially configured as high-order address lines or chip-selects. Table 21 shows the correspondence between DATA[7:3] and the reset configuration of CS[10:6]/ADDR[23:19]. CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect. Table 22 shows CSPAR1 pin assignments. NOTES: 1. Refer to Table 21 for CSPAR1 reset state information. Table 20 CSPAR0 Pin Assignments CSPAR0 Field Chip-Select Signal Alternate Signal Discrete Output CS5PA[1:0] CS5 FC2 PC2 CS4PA[1:0] CS4 FC1 PC1 CS3PA[1:0] CS3 FC0 PC0 CS2PA[1:0] CS2 BGACK — CS1PA[1:0] CS1 BG — CS0PA[1:0] CS0 BR — CSBTPA[1:0] CSBOOT —— CSPAR1 — Chip-Select Pin Assignment Register 1 $YFFA46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CS10PA[1:0] CS9PA[1:0] CS8PA[1:0] CS7PA[1:0] CS6PA[1:0] RESET: 0 0 0 0 0 0 DATA71 1 DATA [7:6]1 1 DATA [7:5]1 1 DATA [7:4]1 1 DATA [7:3]1 1 Table 21 Reset Pin Function of CS[10:6] Data Bus Pins at Reset Chip-Select/Address Bus Pin Function DATA7 DATA6 DATA5 DATA4 DATA3 CS10/ ADDR23 CS9/ ADDR22 CS8/ ADDR21 CS7/ ADDR20 CS8/ ADDR19 11111 CS10 CS9 CS8 CS7 CS6 1111 0 CS10 CS9 CS8 CS7 ADDR19 111 0 X CS10 CS9 CS8 ADDR20 ADDR19 11 0 X X CS10 CS9 ADDR21 ADDR20 ADDR19 1 0 X X X CS10 ADDR22 ADDR21 ADDR20 ADDR19 0 XXXX ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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