SPMC68CK338CPV14 datasheet(92/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

IN2 — Clock Input Pin Status

This read-only status bit reflects the logic state of the clock input pin. Writing to this bit has no effect,

nor does reset.

NOTE

The clock input of MCSM2 is internally connected to I/O pin CTD27 for DASM27

and will read the state of that pin. The clock inputs of MCSM30 and MCSM31 are

internally connected to I/O pin CTD5 for DASM5 and will read the state of that pin.

IN1 — Modulus Load Input Pin Status

This read-only status bit reflects the logic state of the modulus load input pin. Writing to this bit has no

effect, nor does reset.

NOTE

The load input of MCSM2 is internally connected to I/O pin CTD29 for DASM29 and

will read the state of that pin. The load input of MCSM30 is internally connected to

I/O pin CTD4 for DASM4 and will read the state of that pin. The load input of

MCSM31 is available externally on the CTM31L pin.

EDGEN, EDGEP — Modulus Load Edge Sensitivity Bits

These read/write control bits select the sensitivity of the edge detection circuitry on the modulus load

pin CTML. Refer to Table 53.

CLK[2:0] — Counter Clock Select

These read/write control bits select one of six internal clock signals (PCLK[1:6]) or one of two external

conditions on the external clock input pin (rising edge or falling edge). The maximum frequency of the

external clock signals is fsys/4. Refer to Table 54.

Table 53 Modulus Load Edge Sensitivity

EDGEN

EDGEP

IN1 Edge Detector Sensitivity

None

Positive edge only

Negative edge only

Positive and negative edge

Table 54 Counter Clock Select

CLK2

CLK1

CLK0

Free-Running Counter Clock Source

000

PCLK1 (fsys ÷ 2 or fsys ÷ 3)

001

PCLK2 (fsys ÷ 4 or fsys ÷ 6)

010

PCLK3 (fsys ÷ 8 or fsys ÷ 12)

011

PCLK4 (fsys ÷ 16 or fsys ÷ 24)

100

PCLK5 (fsys ÷ 32 or fsys ÷ 48)

101

PCLK6 (fsys ÷ 64 or fsys ÷ 768)

External clock input, falling edge

External clock input, rising edge

Freescale Semiconductor, Inc.

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