SPMC68CK338CPV14 datasheet(69/133 Pages) FREESCALE

69 / 133 page

MC68CK338

MOTOROLA

MC68CK338TS/D

SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM

has read-only access.

Bits [15:11] — Not Implemented

LOOPQ — QSPI Loop Mode

0 = Feedback path disabled

1 = Feedback path enabled

LOOPQ controls feedback on the data serializer for testing.

HMIE — HALTA and MODF Interrupt Enable

0 = HALTA and MODF interrupts disabled

1 = HALTA and MODF interrupts enabled

HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR.

HALT — Halt

0 = Halt not enabled

1 = Halt enabled

When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can

later be restarted.

SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU

reads this register to obtain status information and writes it to clear status flags.

SPIF — QSPI Finished Flag

0 = QSPI not finished

1 = QSPI finished

SPIF is set after execution of the command at the address in ENDQP[3:0].

MODF — Mode Fault Flag

0 = Normal operation

1 = Another SPI node requested to become the network SPI master while the QSPI was enabled

in master mode (SS input taken low).

The QSPI asserts MODF when the QSPI is the serial master (MSTR = 1) and the SS input pin is negat-

ed by an external driver.

HALTA — Halt Acknowledge Flag

0 = QSPI not halted

1 = QSPI halted

HALTA is asserted when the QSPI halts in response to CPU assertion of HALT.

Bit 4 — Not Implemented

SPCR3 — QSPI Control Register

$YFFC1E

LOOPQ

HMIE

HALT

SPSR

RESET:

SPSR — QSPI Status Register

$YFFC1F

SPCR3

SPIF

MODF

HALTA

CPTQP[3:0]

RESET:

Freescale Semiconductor, Inc.

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