SPMC68CK338CPV14 datasheet(91/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

6.8.1 MCSM Registers

The MCSM contains a status/interrupt/control register, a counter, and a modulus latch. All unused bits

and reserved address locations return zero when read. Writing to unused bits and reserved address

locations has no effect. The CTM6 contains three MCSMs, each with its own set of registers.

COF — Counter Overflow Flag

This status flag indicates whether or not a counter overflow has occurred. An overflow of the MCSM

counter is defined to be the transition of the counter from $FFFF to $xxxx, where $xxxx is the value con-

tained in the modulus latch. If the IL[2:0] field is non-zero, an interrupt request is generated when the

COF bit is set.

0 = Counter overflow has not occurred

1 = Counter overflow has occurred

This flag is set only by hardware and cleared only by software or by a system reset. To clear the flag,

the software must first read the register with COF set to one, then write a zero to the bit. COF is cleared

only if no overflow occurs between the read and write operations.

IL[2:0] — Interrupt Level

Setting IL[2:0] to a non-zero value causes the MCSM to request an interrupt of the selected level when

the COF bit sets. If IL[2:0] = %000, no interrupt will be requested when COF sets. These bits can be

read or written at any time and are cleared by reset.

IARB3 — Interrupt Arbitration Bit 3

This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-

quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-

tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same

priority. The IARB3 bit is cleared by reset. Refer to 6.4.1 BIUSM Registers for more information on

IARB[2:0].

DRV[A:B] — Drive Time Base Bus

This bit field contains read/write bits that control the connection of the MCSM to time base buses A and

B. These bits are cleared by reset. Refer to Table 52.

WARNING

Two time base buses should not be driven at the same time.

MCSM2SIC — MCSM2 Status/Interrupt/Control Register

$YFF410

MCSM30SIC — MCSM30 Status/Interrupt/Control Register

$YFF4F0

MCSM31SIC — MCSM31 Status/Interrupt/Control Register

$YFF4F8

COF

IL[2:0]

IARB3

DRVA

DRVB

IN2

IN1

EDGEN EDGEP

CLK[2:0]

RESET:

Table 52 Drive Time Base Bus Field

DRVA

DRVB

Bus Selected

No time base bus is driven

Time base bus B is driven

Time base bus A is driven

Both time base buses A and B are driven

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