SPMC68CK338CPV14 datasheet(74/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any time.

The SCI can modify RWU in some circumstances. In general, interrupts enabled by these control bits

are cleared by reading SCSR, then reading (for receiver status bits) or writing (for transmitter status bits)

SCDR.

Bit 15 — Not Implemented

LOOPS — Loop Mode

0 = Normal SCI operation, no looping, feedback path disabled

1 = Test SCI operation, looping, feedback path enabled

LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter

output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver

must be enabled before entering loop mode.

WOMS — Wired-OR Mode for SCI Pins

0 = If configured as an output, TXD is a normal CMOS output.

1 = If configured as an output, TXD is an open-drain output.

WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is

used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect.

ILT — Idle-Line Detect Type

0 = Short idle-line detect (start count on first one)

1 = Long idle-line detect (start count on first one after stop bit(s))

PT — Parity Type

0 = Even parity

1 = Odd parity

When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans-

mitter.

PE — Parity Enable

0 = SCI parity disabled

1 = SCI parity enabled

PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-

ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.

When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-

sults in either seven or eight bits of user data, depending on the condition of M bit. Table 44 lists the

available choices.

SCCR1 — SCI Control Register 1

$YFFC0A

LOOPS WOMS

ILT

WAKE

TIE

TCIE

RIE

ILIE

RWU

SBK

RESET:

Table 44 Parity Enable Data Bit Selection

Result

8 data bits

7 data bits, 1 parity bit

9 data bits

8 data bits, 1 parity bit

Freescale Semiconductor, Inc.

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