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SPMC68CK338CPV14 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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SPMC68CK338CPV14 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 133 page ![]() MC68CK338 MOTOROLA MC68CK338TS/D 11 Data Strobe DS Indicates that an external device should place valid data on the data bus during a read cycle and that valid data has been placed on the bus by the CPU during a write cycle Data and Size Acknowledge DSACK[1:0] Acknowledges to the SIML that data has been received for a write cycle, or that data is valid on the data bus for a read cycle Development Serial In, Out, Clock DSI, DSO, DSCLK Serial I/O and clock for background debugging mode Function Codes FC[2:0] Identify processor state and current address space Freeze FREEZE Indicates that the CPU has entered background mode Halt HALT Suspend external bus activity Instruction Pipeline IFETCH, IPIPE Indicate instruction pipeline activity Interrupt Request Level IRQ[7:1] Request interrupt service from the CPU Master In Slave Out MISO Serial input to QSPI in master mode; serial output from QSPI in slave mode Clock Mode Select MODCLK Selects system clock source Master Out Slave In MOSI Serial output from QSPI in master mode; serial input to QSPI in slave mode Port C PC[6:0] SIML digital output signals Peripheral Chip Select PCS[3:0] QSPI peripheral chip selects Port E PE[7:0] SIML digital input or output port signals Port F PF[7:0] SIML digital input or output port signals Port QS PQS[7:0] QSM digital I/O port signals Quotient Out QUOT Provides the quotient bit of the polynomial divider Reset RESET System reset Read-Modify-Write Cycle RMC Indicates an indivisible read-modify-write instruction Read/Write R/W Indicates the direction of data transfer on the bus SCI Receive Data RXD Serial input to the SCI QSPI Serial Clock SCK Clock output from QSPI in master mode; clock input to QSPI in slave mode Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle Slave Select SS Causes serial transmission when QSPI is in slave mode. Causes mode fault in master mode Three-State Control TSC Places all output drivers in a high-impedance state SCI Transmit Data TXD Serial output from the SCI External Filter Capacitor XFC Connection for external phase-locked loop filter capacitor Table 6 MCU Signal Function (Continued) Signal Name Mnemonic Function Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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