SPMC68CK338CPV14 datasheet(38/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

This field only affects the response of chip-selects and does not affect interrupt recognition by the CPU.

Any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle.

AVEC — Autovector Enable

0 = External interrupt vector enabled

1 = Autovector enabled

This field selects one of two methods of acquiring an interrupt vector number during an external interrupt

acknowledge cycle.

If the chip-select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and

the AVEC field is set to one, the chip-select circuit generates an internal AVEC signal in response to an

external interrupt cycle, and the SIML supplies an automatic vector number. Otherwise, the vector num-

ber must be supplied by the requesting device. An internal autovector is generated only in response to

interrupt requests from the SIML IRQ pins. Interrupt requests from other IMB modules are ignored.

The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because

of ECLK synchronization.

3.6.5 Port C Data Register

Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is as-

signed as a discrete output, the value in this register appears at the output. This is a read/write register.

Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.

3.7 General-Purpose Input/Output

SIML pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de-

scribe registers that control the ports.

Table 28 Interrupt Priority Level Field Encoding

IPL[2:0]

Interrupt Priority Level

000

Any Level

001

010

011

100

101

110

111

PORTC — Port C Data Register

$YFFA41

NOT USED

PC6

PC5

PC4

PC3

PC2

PC1

PC0

RESET:

Freescale Semiconductor, Inc.

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