SPMC68CK338CPV14 datasheet(17/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

Figure 6 System Clock Oscillator Circuit

When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty

cycle of the input is critical, especially at operating frequencies close to maximum. The relationship be-

tween clock signal duty cycle and clock signal period is expressed:

When the system clock signal is applied directly to the EXTAL pin (PLL is disabled, MODCLK = 0 during

reset), or the clock synthesizer reference frequency is supplied by a source other than a crystal (PLL

enabled, MODCLK = 1 during reset), the XTAL pin must be left floating. In either case, the frequency of

the signal applied to EXTAL may not exceed the maximum system clock frequency (PLL disabled) or

the maximum clock synthesizer reference frequency (PLL enabled).

3.3.2 Clock Synthesizer Operation

VDDSYN is used to power the clock circuits when the phase-locked loop is used. A separate power

source increases MCU noise immunity and can be used to run the clock when the MCU is powered

down. A quiet power supply must be used as the VDDSYN source. Adequate external bypass capacitors

should be placed as close as possible to the VDDSYN pin to assure stable operating frequency. When

an external system clock signal is applied and the PLL is disabled, VDDSYN should be connected to the

VDD supply. Refer to the SIM Reference Manual (SIMRM/AD) for more information regarding system

clock power supply conditioning.

A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty

cycle, the VCO frequency (fVCO) is either two or four times the system clock frequency, depending on

the state of the X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider

controls the frequency of one input to a phase comparator. The other phase comparator input is the

reference signal connected to the EXTAL pin. The comparator generates a control signal proportional

to the difference in phase between the two inputs. The signal is low-pass filtered and used to correct

the VCO output frequency.

Filter circuit implementation can vary, depending upon the external environment and required clock sta-

bility. Figure 7 shows a recommended system clock filter network. XFC pin leakage must be kept within

specified limits to maintain optimum stability and PLL performance.

An external filter network connected to the XFC pin is not required when an external system clock signal

is applied and the PLL is disabled. The XFC pin must be left floating in this case.

338 OSCILLATOR

EXTAL

XTAL

10M

Ω*

4.7 k

Ω*

22 pF*

VSSI

RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768 kHZ CRYSTAL.

SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.

Minimum External Clock Period

Minimum External Clock High/Low Time

50 %

Percentage Variation of External Clock Input Duty Cycle

–

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Freescale Semiconductor, Inc.

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