SPMC68CK338CPV14 datasheet(34/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

Port size determines the way in which bus transfers to external addresses are allocated. Port size of

eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. Port size and transfer

size affect how the chip-select signal is asserted. Refer to 3.6.4 Option Registers for more information.

Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin.

These pins have weak internal pull-up drivers, but can be held low by external devices. Either 16-bit

chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the

boot ROM select pin (CSBOOT) are disabled out of reset.

The CSBOOT signal is normally enabled out of reset. The state of the DATA0 line during reset deter-

mines what port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver

or by an external pull-up device), 16-bit width is selected. If DATA0 is held low, 8-bit port size is selected.

A pin programmed as a discrete output drives an external signal to the value specified in the pin data

vides ECLK output rather than a discrete output signal.

When a pin is programmed for discrete output or alternate function, internal chip-select logic still func-

tions and can be used to generate DSACK or AVEC internally on an address and control signal match.

3.6.3 Base Address Registers

Each chip-select has an associated base address register. A base address is the lowest address in the

block of addresses enabled by a chip-select. Block size is the extent of the address block above the

base address. Block size is determined by the value contained in a BLKSZ field. Multiple chip-selects

may be assigned to the same block of addresses so long as each chip-select uses the same number

of wait states.

The BLKSZ field determines which bits in the base address field are compared to corresponding bits on

the address bus during an access. Provided other constraints determined by option register fields are

also satisfied, when a match occurs, the associated chip-select signal is asserted.

After reset, the MCU fetches the address of the first instruction to be executed from the reset vector,

located beginning at address $000000 in program space. To support bootstrap operation from reset,

the base address field in CSBARBT has a reset value of all zeros. A memory device containing the reset

vector and an initialization routine can be automatically enabled by CSBOOT after a reset. The block

size field in CSBARBT has a reset value of one Mbyte.

Table 22 CSPAR1 Pin Assignments

CSPAR1 Field

Chip-Select Signal

Alternate Signal

Discrete Output

CS10PA[1:0]

CS10

ADDR23

ECLK

CS9PA[1:0]

CS9

ADDR22

PC6

CS8PA[1:0]

CS8

ADDR21

PC5

CS7PA[1:0]

CS7

ADDR20

PC4

CS6PA[1:0]

CS6

ADDR19

PC3

CSBARBT — Chip-Select Base Address Register Boot ROM

$YFFA48

ADDR

BLKSZ[2:0]

RESET:

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