SPMC68CK338CPV14 datasheet(37/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

SPACE[1:0] — Address Space

Use this option field to select an address space for the chip-select logic. The CPU32L normally operates

in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space. Table 27

shows address space bit encodings.

IPL[2:0] — Interrupt Priority Level

If the space field is set for CPU space, chip-select logic can be used for interrupt acknowledge. During

an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the value

in IPL[2:0]. If the values are the same, a chip-select is asserted, provided that other option register con-

ditions are met. Table 28 shows IPL[2:0] encoding.

Table 26 DSACK Field Encoding

DSACK[3:0]

Clock Cycles Required

Per Access

Wait States

Per Access

0000

0 Wait States

0001

1 Wait State

0010

2 Wait States

0011

3 Wait States

0100

4 Wait States

0101

5 Wait States

0110

6 Wait States

0111

7 Wait States

1000

8 Wait States

1001

9 Wait States

1010

10 Wait States

1011

11 Wait States

1100

12 Wait States

1101

13 Wait States

1110

Fast Termination

1111

—

External DSACK

Table 27 Address Space Bit Encodings

SPACE[1:0]

Address Space

CPU Space

User Space

Supervisor Space

Supervisor/User Space

Freescale Semiconductor, Inc.

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