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SPMC68CK338CPV14 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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SPMC68CK338CPV14 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 133 page ![]() MC68CK338 MOTOROLA MC68CK338TS/D 77 NF — Noise Error Flag 0 = No noise detected on the received data 1 = Noise occurred on the received data NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If none of the three samples are the same logic level, the majority value is used for the received data value, and NF is set. NF is not set until an entire frame is received and RDRF is set. FE — Framing Error Flag 0 = No framing error on the received data. 1 = Framing error or break occurred on the received data. FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss a framing error if RXD happens to be at logic level one at the time the stop bit is expected. PF — Parity Error Flag 0 = No parity error on the received data 1 = Parity error occurred on the received data PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and RDRF is set. SCDR contains two data registers at the same address. The receive data register is a read-only register that contains data received by the SCI. The data comes into the receive serial shifter and is transferred to the receive data register. The transmit data register is a write-only register that contains data to be transmitted. The data is first written to the transmit data register, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect. SCDR — SCI Data Register $YFFC0E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 RESET: 0 0 0 0 0 0 0 U U U U U U U U U Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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