SPMC68CK338CPV14 datasheet(47/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

A. The CPU finishes higher priority exception processing or reaches an instruction boundary.

B. The processor state is stacked. The S bit in the status register is set, establishing supervisor

access level, and bits T1 and T0 are cleared, disabling tracing.

C. The interrupt acknowledge cycle begins:

FC[2:0] are driven to %111 (CPU space) encoding.

The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111,

which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]

= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;

and ADDR0 = %1.

The request level is latched from the address bus into the interrupt priority mask field in the

status or condition code register.

D. Modules that have requested interrupt service decode the priority value on ADDR[3:1]. If

request priority is the same as acknowledged priority, arbitration by IARB contention takes

place.

E. After arbitration, the interrupt acknowledge cycle is completed in one of the following ways:

When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR,

and the CPU generates the spurious interrupt vector number.

The dominant interrupt source supplies a vector number and DSACK signals appropriate

to the access. The CPU acquires the vector number.

The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source

or the pin can be tied low), and the CPU generates an autovector number corresponding

to interrupt priority.

The bus monitor asserts BERR and the CPU32L generates the spurious interrupt vector

number.

F. The vector number is converted to a vector address.

G. The content of the vector address is loaded into the PC, and the processor transfers control to

the exception handler routine.

3.10 Factory Test Block

The test submodule supports scan-based testing of the various MCU modules. It is integrated into the

SIML to support production testing.

Test submodule registers are intended for Motorola use. Register names and addresses are provided

to indicate that these addresses are occupied.

SIMLTR — System Integration Module Test Register

$YFFA02

SIMLTRE — System Integration Module Test Register (E Clock)

$YFFA08

TSTMSRA — Master Shift Register A

$YFFA30

TSTMSRB — Master Shift Register B

$YFFA32

TSTSC — Test Module Shift Count

$YFFA34

TSTRC — Test Module Repetition Count

$YFFA36

CREG — Test Module Control Register

$YFFA38

DREG — Test Module Distributed Register

$YFFA3A

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SPMC68CK338CPV14 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

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