SPMC68CK338CPV14 datasheet(16/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

3.3 System Clock

The system clock in the SIML provides timing signals for the IMB modules and for an external peripheral

bus. Because the MCU is a fully static design, register and memory contents are not affected when the

clock rate changes. System hardware and software support changes in clock rate during operation.

The system clock signal can be generated in one of two ways. An internal phase-locked loop can

synthesize the clock from a reference frequency, or the clock signal can be input directly from an

external source. Keep these clock sources in mind while reading the rest of this section. Figure 5 is a

block diagram of the system clock.

Figure 5 System Clock Block Diagram

3.3.1 Clock Sources

The state of the clock mode (MODCLK) pin during reset determines the system clock source. When

MODCLK is held high during reset, the clock synthesizer generates a clock signal from a reference

frequency connected to the EXTAL pin. The clock synthesizer control register (SYNCR) determines

operating frequency and mode of operation. When MODCLK is held low during reset, the clock

synthesizer is disabled and an external system clock signal must be applied. The SYNCR control bits

have no effect.

The input clock is referred to as “fref”, and can be either a crystal or an external clock source. The output

of the clock system is referred to as “fsys”. Ensure that fref and fsys are within normal operating limits.

The reference frequency for this MCU is typically 32.768 kHz, but can range from 25 kHz to 50 kHz. To

generate a reference frequency using the crystal oscillator, a reference crystal must be connected be-

tween the EXTAL and XTAL pins. Figure 6 shows a recommended circuit.

16/32 PLL BLOCK

PHASE

COMPARATOR

LOW-PASS

FILTER

VCO

CRYSTAL

OSCILLATOR

SYSTEM

CLOCK

SYSTEM CLOCK CONTROL

FEEDBACK DIVIDER

EXTAL

XTAL

XFC

CLKOUT

MODCLK

VDDSYN

Freescale Semiconductor, Inc.

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