MFS2401AVBA0ES datasheet(16/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

7.3 INIT state machine

From any

Mx state

VBOS < VBOS_por

Or VDIG < VDIG_por

Or VDIG > VDIG_ov

VBOS > VBOS_por

And VDIG > VDIG_por

And VDIG < VDIG_ov

Go2INIT = 1

And Mode = NORMAL (M9)

Legend: Green: Safety related device action, Black: Device state

Cyclic CRC check disabled

INIT registers unlocked

WD infinite period writing unlocked

Cyclic CRC check enabled

INIT registers locked

WD infinite period writing locked

WD_OK

INIT_1

INIT state

INIT_0

POR

aaa-046837

Figure 9. Simplified INIT state diagram

At power-on reset (POR), the device is automatically in INIT state. In this state, the INIT registers (FS_I_xxxxx)

are available for writing and configuring the device safety features and reactions. The cyclic CRC check that

protects these registers is disabled. Also in this mode, the watchdog period can be configured as infinite, which

is equivalent to disabling the watchdog, for MCU programming for example. See Section 7.6.

Initialization should be done within 256 ms after RSTB release to avoid watchdog errors. Initialization

phase is closed by first correct watchdog refresh. The INIT registers, as well as the infinite watchdog period

configuration, are then protected against write access. The cyclic CRC check on the INIT registers is activated,

and occurs every 5 ms.

The INIT state can be accessed again from Normal mode by sending a GO2INIT request by SPI.

The device will not enter the INIT state again when waking up from LPON or LPOFF states, or when restarting

from Fail-safe state.

Note: If the device goes in LPON or LPOFF or Fail-safe mode while in INIT state, the device stays in INIT

state, which can lead to misconfiguration of the device. It is recommended to read the INIT_S status bit in

M_STATUS register before going to LPON or LPOFF mode, and to go only if the device is no longer in INIT

state.

7.4 Power sequencing

V1 is the first regulator to start automatically in SLOT_0, then V3 regulator and HVIO1 (if configured) start

following the OTP power sequencing configuration. Three slots are available, from SLOT_0 to SLOT_2, to

program the startup sequence of V3 regulator, as well as HVIO1 release or assertion. A power-up slot (Tslot)

lasts at least 500 µs. If V1 configured soft-start is longer than 500 µs, SLOT_0 will end once V1 soft-start is

done.

The power-up sequence starts at SLOT_0 toward SLOT_2. The power-down sequence is executed in reverse

order, starting at SLOT_2 toward SLOT_0.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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