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MFS2401AVBA0ES Datasheet(PDF) 92 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 92 Page - NXP Semiconductors |
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92 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description Request to enable V3 0 No effect (Regulator remain in its current state) 1 Request to enable V3 1 V3EN POR, Self-clear Configure V3 state in LPON mode 0 Follow the power down slot configuration 1 Keep V3 ON in LPON if V3 was already ON in NORMAL mode 2 V3ON_LPON POR Request to disable V1 0 No effect (Regulator remain in its current state) 1 Request to disable V1 6 V1DIS POR, Self-clear Request to enable V1 0 No effect (Regulator remain in its current state) 1 Request to enable V1 7 V1EN POR, Self-clear Select BUCK slew rate when the High Side turns ON 000 HS rising slew rate is 20 ns (for 450 kHz only) 001 HS rising slew rate is 20 ns (for 450 kHz only) 010 HS rising slew rate is 15 ns (for 450 kHz only) 011 HS rising slew rate is 10 ns 100 HS rising slew rate is 6.3 ns 101 HS rising slew rate is 5 ns 110 HS rising slew rate is 3 ns 111 HS rising slew rate is 2 ns 8 to 10 BUCK_SRHSON POR or OTP Fuse load Select BUCK slew rate when the High Side turns OFF 00 HS falling slew rate is 20 ns (for 450 kHz only) 01 HS falling slew rate is 15 ns (for 450 kHz only) 10 HS falling slew rate is 10 ns 11 HS falling slew rate is 5 ns 11 to 12 BUCK_SRHSOFF POR or OTP Fuse load Table 71. M_REG_CTRL register bit description...continued 22.8 M_REG2_CTRL Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 GO2DFLT GO2DVS Read 0 0 0 0 0 VV1_BUCK_S 0 0 Reset 0 0 0 0 0 0 0 0 Table 72. M_REG_CTRL register bit allocation FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 92 / 151 |
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