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MFS2401AVBA0ES Datasheet(PDF) 75 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 75 Page - NXP Semiconductors |
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75 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver TA = -40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Static electrical characteristics LIMP0VIL Low-level Input voltage LIMP0_TH_SEL = 0 LIMP0_TH_SEL = 1 - - - - 0.7 2 V LIMP0VIH High-level Input voltage LIMP0_TH_SEL = 0 LIMP0_TH_SEL = 1 1.5 3 - - - - V LIMP0VOL Low-level output voltage (I = 2.0 mA) - - 0.4 V LIMP0RPD Internal pulldown resistor 1 2 4 MΩ LIMP0ILIM Current limitation 4 - 22 mA Dynamic electrical characteristics LIMP0TFB Feedback filtering time 8 10 15 µs LIMP0TSC Short- to high-detection timer 500 650 800 µs LIMP0TFALL Fall time (pullup to VSUP = 14 V, 10 nF output capacitor) - - 25 µs External components External pullup resistor to VDDIO (nominal) - 5.1 - kΩ LIMP0RPU External pullup resistor to VSUP (nominal) - 10 - kΩ LIMP0RSER External serial resistor (optional, 0805 package size) - 5.1 - kΩ LIMP0COUT1 External output capacitor (close to the pin) - 10 - nF LIMP0COUT2 External output capacitor (optional, after the serial resistor) - 22 - nF Table 47. LIMP0 electrical characteristics 19.6.3 LIMP0 as a safety output release When the fail-safe output LIMP0 is asserted low by the device because a fault, some conditions must be validated before allowing the LIMP0 pin to be released by the device. These conditions are: • No fault affecting LIMP0 reported • Fault error counter = 0 • Device in Normal mode • Device not in INIT mode • FS_LIMP0_REL register filled with the correct value, depending on current WD_TOKEN[15:0], (WD_TOKEN[15:8] with LSB and MSB inverted, then complemented) 19.6.4 LIMP0 as a GPO When LIMP0 is not used as a safety output, it can be used as a general purpose output (GPO). To use LIMP0 as a GPO, LIMP0_EN_OTP bit must be set to 0 and the MCU must configure LIMP0_GPO = 1 during INIT phase. The pin is set to low level by setting the LIMP0_REQ bit and set to high level (biased by the external pull up) by setting the LIMP0_REL bit. 19.7 Analog built-in self-test (ABIST) The FS24 provides an analog built-in self-test (ABIST) to verify the correct functionality of the voltage monitoring functions. The ABIST is executed on demand, after an SPI request from the MCU. ABIST can only be launched from Normal mode. A status bit ABIST_READY is provided to notify that ABIST is available and ready to be launched. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 75 / 151 |
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