MFS2401AVBA0ES datasheet(79/151 Pages) NXP

79 / 151 page

NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

20.1.1 Cyclic redundant check

An 8-bit CRC is required for each write and read SPI command. Computation of a cyclic-redundancy

check is derived from the mathematics of polynomial division, modulo two. The CRC polynomial used is

x^8+x^4+x^3+x^2+1 (identified by 0x1D) with a seed value of hexadecimal '0xFF'.

Figure 47 is an example of CRC encoding HW implementation:

aaa-046864

1*1

0*X

1*X2

1*X3

1*X4

0*X5

0*X6

0*X7

1*X8

Input

Data

Figure 47. CRC encoder example

The effect of CRC encoding procedure is shown in Table 53. The seed value is appended into the most

significant bits of the shift register.

Seed

Read/Write

Data_MSB

Data_LSB

0xFF

Bits[31:25]

Bit[24]

Bits[23:16]

Bits[15:8]

Table 53. Data preparation for CRC encoding

Seed

…

… padded with the message to encode

… padded with 8 zeros

Table 54. Data preparation for CRC encoding

1. Using a serial CRC calculation method, the transmitter rotates the seed and data into the least significant

bits of the shift register.

2. During the serial CRC calculation, the seed and the data bits are XOR compared with the polynomial data

bits. When the MSB is logic 1, the comparison result is loaded in the register, otherwise the data bits are

simply shifted.

Note: The 32-bits message to be processed must have the bits corresponding to the CRC byte all equal to

zero (00000000).

3. Once the CRC is calculated, it replaces the CRC byte initially set to all zeros and is transmitted.

Use the following steps for CRC decoding:

Procedure for CRC decoding

1. The seed value is loaded into the most significant bits of the receive register.

2. Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least

significant bits of the shift register in the order received (MSB first).

3. When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the

CRC check result.

• If the shift register contains all zeros, the CRC is correct.

• If the shift register contains a value other than zero, the CRC is incorrect.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

Document feedback

79 / 151

MFS2401AVBA0ES Datasheet(PDF) 79 Page - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL