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MFS2401AVBA0ES Datasheet(PDF) 17 Page - NXP Semiconductors

Part # MFS2401AVBA0ES
Description  Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 17 Page - NXP Semiconductors

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NXP Semiconductors
FS2400
Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
All regulators not assigned in any slot are not started during the power-up sequence. These regulators can be
started later when the main state machine is in Normal mode with an SPI command to write in M_REG_CTRL
register if they were enabled by OTP.
When waking from LPON mode, the TSLOT timer can be skipped from SLOT_0 to SLOT_1 and from SLOT_2
to Normal mode by setting the SLOT_BYP bit to 1. During the power-down sequence, when the SLOT_BYP bit
is set to 1, the TSLOT timer between SLOT_2 and SLOT_1 will be bypassed, as well.
aaa-046838
Power up
Power down
From
WAIT VSUP
To
NORMAL
SLOT_0
VSUP > VSUP_UV
(TSLOT or SLOT_BYP) and
V1 Soft-Start/DVS done
TSLOT
TSLOT
SLOT_BYP = 1
SLOT_1
SLOT_2
SLOT_BYP = 1
From
NORMAL
To
LPON
To
LPOFF
SLOT_2
Go2LPON = 1 or Go2LPOFF = 1
TSLOT_DOWN
TSLOT_DOWN
2 ms
TRAMP_DOWN_V1 +
TBOS2V1
TBOS2V1 = 10 µs if VBOS2V1_SW_LP_EN_OTP = 0
TBOS2V1 = 1 ms if VBOS2V1_SW_LP_EN_OTP = 1
Here SLOT_BYP = 1 is only applicable when
waking up from LPON
SLOT_1
SLOT_0
Figure 10. Power sequencing
 
FS2400
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 23 October 2024
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