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MFS2401AVBA0ES Datasheet(PDF) 47 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver state is inverted when the configured slot starts. At power down, the pin goes back to its default value when the configured slot starts. See Figure 31 as an example of HVIO pins configuration, with HVIO1 default state low and assigned to SLOT1. aaa-046848 VBAT HVIO1 (default 0) OTP Loaded Slot 0 Tslot Tslot Tslot Slot 1 Slot 2 Vsup > Vsup_UV Figure 31. Example of HVIO1 pin configuration in the slots, at power up 16.2.3 Electrical characteristics TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit HVIO1 HVIO1VIL Digital low-input voltage threshold (falling) - - 2 V HVIO1VIH Digital high-input voltage threshold (rising) 2.97 - - V HVIO1HYST Hysteresis 100 - 400 mV HVIO1VOL Low-output level (IOUT = 2 mA) - - 0.4 V HVIO1ILIM Current limitation 4 - 22 mA IIN_HVIO1 Input current on HVIO1 pin (No pull down or pull up) -5 - 5 μA RPD_HVIO1 Pulldown resistance 100 200 400 kΩ RPU_HVIO1 Pullup resistance 100 200 400 kΩ THVIO1_FLT Wake-up filtering time • HVIO1_DGLT = 0 • HVIO1_DGLT = 1 12 50 15 65 20 80 μs THVIO1_FALL Fall time using open drain (external pullup at VUP = 14 V, COUT_HVIO1 = 10 nF) - - 30 μs THVIO1_WU Time between HVIO1 rising and V1 switching from PFM to PWM mode when HVIO1 configured as “mode selection” • LOAD_OTP_BYP = 0 • LOAD_OTP_BYP = 1 - - 150 50 - - μs Table 19. HVIO1 electrical characteristics 16.3 INTB INTB is an open-drain output pin with internal pullup to VDDIO. This pin generates a pulse when an internal interrupt occurs to inform the MCU. Each interrupt can be masked by setting the corresponding inhibit interrupt. An INTB pulse can be required for diagnosis by the MCU setting the SPI INTB_REQ bit in M_SYS_CFG SPI register. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 47 / 151 |
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