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MFS2401AVBA0ES Datasheet(PDF) 46 Page - NXP Semiconductors

Part # MFS2401AVBA0ES
Description  Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 46 Page - NXP Semiconductors

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NXP Semiconductors
FS2400
Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
16.2 HVIO1
HVIO1 pin is a high-voltage input/output. It can be used as input (as a wake-up source, a mode selection pin or
an external device monitoring pin) or as open-drain output.
aaa-049160
SPI
HVIO pin
status
RPU_HVIO1
RPD_HVIO1
HVIO1
HVIO1
VSUP
Control
Figure 30. HVIO1 pin
16.2.1 HVIO1 used as input
The HVIO1 pin can be used as a simple wake-capable input. In this case, when the device is in Normal mode,
any event on HVIO1 pin generates a flag (HVIO1_I), when not masked (HVIO1_M). In Low-power modes,
wake-up event can be generated on level (high or low) depending on HVIO1_WUCFG[1:0] bits.
Using the same bits, the MCU can configure HVIO1 as "mode selection". When configured as mode selection,
HVIO1 pin voltage level commands the transition between Normal mode and LPON (Low-power on). A falling
edge makes FS2400 switch from Normal to LPON mode, a rising edge makes FS2400 switch from LPON to
Normal mode.
When used as a wake-up source, wake-up filtering time is configurable by SPI using HVIO1_DGLY bit.
Internal pulldown and pullup resistors can be enabled, disabled or configured as cell repeater as per
HVIO1PUPD_OTP[1:0] bits.
Note: Cell-repeater configuration is used to reduce the current consumption. In this configuration, the pullup or
pulldown selection follows the state of the internal buffer output after filtering. If the buffer output is low, pulldown
resistor is selected. If the buffer output is high, the pullup resistor is selected.
When an HVIO pin is used as a global input pin, an R - C protection is required. See Section 11.
HVIO1 can also be configured as ERRMON input, to provide MCU or external device error detection. See
Section 19.4.
16.2.2 HVIO1 used as output
HVIO1 can be configured as open-drain output by OTP via HVIO1_OUT_EN_OTP bits. In this case, the output
state can be controlled by SPI using HVIO1HI and HVIO1LO control bits.
The default output state can be configured by OTP using HVIO1_OUT_DFLT_OTP. HVIO1 can also be
assigned to one of the slots (SLOT0/1/2) by OTP using HVIO1_SLOT_POL_OTP. In this case, during power up,
the pin follows the default state as soon as the OTP configuration is loaded in the mirror registers, and the pin
FS2400
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 23 October 2024
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