MFS2401AVBA0ES datasheet(60/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

19 Safety

19.1 Functional description

The FS24 includes multiple safety mechanisms to guarantee the functional safety of the system and reach up

to ASIL B level. Safety features are configurable, either by OTP or by SPI, allowing scalability depending on the

application needs. FS24 also provides an on-demand ABIST to cover latent faults.

aaa-046855

RESET

DRIVER

LIMP0

DRIVER

OTP

ABIST

WATCHDOG

V0MON

V1MON

V3MON

SAFETY FEATURES

RSTB

VMON_EXT

ERRMON

LIMP0

DIGITAL

STATE MACHINE

VOLTAGE

SUPERVISION

SYSTEM FAILURE

MONITORING

Figure 38. Fail-safe features block diagram

19.2 Watchdog

A watchdog is implemented through the SPI bus to continuously check the microcontroller software activity

and its ability to perform basic computing. FS24 checks by awaiting a specific answer from the microcontroller

during a predefined period called the watchdog window. The first half of the watchdog window is said closed

and the second half is said open.

A good watchdog refresh is a good watchdog answer during the open window. A bad watchdog refresh is

a bad watchdog answer during the open window, no watchdog refresh during the open window or a good

watchdog answer during the closed window. After a good or a bad watchdog refresh, a new window period

starts immediately for the microcontroller to keep the synchronization with the windowed watchdog. The first

good watchdog refresh closes the initialization phase of the FS24. Then the watchdog window is running and

the microcontroller must refresh the watchdog in the open window of the watchdog window period.

The watchdog functionality can be enabled or disabled by OTP with WD_INF_OTP bit. The duration of the

watchdog window is configurable from 1 ms to 16384 ms with the WDW_PERIOD[3:0] SPI bits. The new

watchdog window is effective after the next watchdog refresh. The watchdog window can be disabled only

during the initialization phase of the FS24. The watchdog disable is effective when the initialization phase is

closed. The watchdog configuration requires the MCU to write in FS_WDW_CFG registers.

In LPON mode, the watchdog stays enabled or is disabled depending on WD_DIS_LPON bit (configurable

during INIT phase). When enabled in LPON, the watchdog operates in Timeout mode.

The watchdog uses two keys, 0x5AB2 (default value after POR) and 0xD564 to validate the answer. The key is

stored in the WD_TOKEN register, and is changed alternatively after each good WD refresh.

The MCU reads the WD_TOKEN register and writes the correct answer (WD_TOKEN register value) through

the SPI in WD_ANSWER register, in the right timing. The WD error counter is incremented when the answer is

wrong or not given at the right moment, or not given at all at the end of the watchdog period.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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