MFS2401AVBA0ES datasheet(76/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

ABIST can be launched for all the voltage monitoring channels at the same time (via LAUNCH_ABIST bit), or

individually (via ABIST_Vxxxx individual bits). An individual diagnostic bit is available for each channel once

the ABIST is done (ABIST_DONE = 1). A CLEAR_ABIST bit is available to clear the diagnostic flags before

launching the next ABIST. The flags have no impact on the safety pins.

If one of the concerned monitored voltage is out of range (OV or UV), the ABIST on demand command is

ignored. While the ABIST is running, the other monitoring functions are kept available.

TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

Symbol

Parameter

Min

Typ

Max

Unit

ABIST

TABIST

ABIST duration for one monitoring channel

µs

Table 48. ABIST electrical characteristics

19.8 Cyclic CRC check

The FS24 provides an 8-bit cyclic CRC check to verify the integrity of the INIT registers (FS_I_xxxx) containing

the safety configuration information (configurable in INIT mode only). This mechanism allows for the detection of

a misconfiguration from the MCU or a bit flip in the INIT registers.

The 8-bit CRC is computed on the result of the concatenation of the following register bits:

• FS_I_OVUV_CFG1[15:0]

• FS_I_OVUV_CFG2[15:0]

• FS_I_ERRMON_LIMP0_CFG[15:0]

• FS_I_FSSM_CFG[15:4]

• FS_I_WD_CFG[15:7]

The calculation to apply on the result of the concatenation is the same as the SPI CRC, using

x^8+x^4+x^3+x^2+1 polynomial. The MCU must write the obtained CRC in the FS_CRC register before closing

the INIT phase, after the modification of the INIT registers.

Once the INIT phase is closed and the device is in Normal mode, the cyclic CRC check is launched

automatically each 5 ms (TCRC) (<FTTI).

Each 5 ms, the device logic recalculates the CRC and compares it to the value stored in FS_CRC register.

If a mismatch is reported, the INIT_CRC_NOK_I bit is set and LIMP0 is asserted depending on its impact

configuration (INIT_CRC_LIMP0_IMPACT).

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

Symbol

Parameter

Min

Typ

Max

Unit

Cyclic CRC check

TCRC

CRC check timing interval

4.75

5.25

Table 49. Cyclic CRC check characteristics

19.9 Clock monitoring

The 1 MHz clock is monitored for stuck-at faults in Normal mode. In case a stuck-at is detected, the two safety

pins RSTB and LIMP0 are asserted.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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