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MFS2401AVBA0ES Datasheet(PDF) 69 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver aaa-046859 Error signal (ERRMON input) FS24 ERRMON_ACK bit LIMP0 Reset counter ERRMON_ACK_TIME ERRMON_ACK_TIME Error acknowledged by MCU. Internal monitoring signal released. No error reported. Error NOT acknowledged by MCU. Error reported at the end of the counter. LIMP0 is asserted Figure 42. External IC monitoring timing diagram TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Description Min Typ Max Unit Electrical characteristics VIH_ERRMON High-level input voltage threshold 0.7 x VDDIO - - V VIL_ERRMON Low-level input voltage threshold - - 0.3 x VDDIO V VIN_HYS_ERRMON Threshold hysteresis 100 - - mV tERRMON_ERR Filtering time 4 6 8 µs tERRMON_ACK_ACC Acknowledgment counter accuracy -10 - 10 % RPD_ERRMON ERRMON pulldown resistor value 200 400 800 kΩ Table 41. External IC monitoring electrical characteristics 19.5 Fault management 19.5.1 Fault error counter The FS24 integrates a configurable fault error counter, which is counting the number of faults related to the device and also caused by external events. The fault error counter starts at 1 after a POR or resuming from LPON or LPOFF. The final value of the fault error counter is used to transition in fail-safe state (all safety pins asserted). The maximum value of this counter is configurable with the FLT_ERR_LIMIT[1:0] bits during the INIT phase. FLT_ERR_LIMIT[1:0] Fault error counter max value configuration Fault error counter intermediate value 00 2 1 01 (default) 6 3 10 8 4 11 12 6 Reset condition POR Table 42. Fault error counter configuration FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 69 / 151 |
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