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MFS2401AVBA0ES Datasheet(PDF) 72 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 72 Page - NXP Semiconductors |
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72 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver In Green, the reaction is configurable by OTP and SPI for RSTB and by SPI for LIMP0 in INIT mode. Mode Fault Source Fault error counter RSTB assertion LIMP0 assertion VxTSD & CONF_TSD_Vx_OTP Max Yes [1] Yes[1] VxMON_OV & CONF_OV_Vx_OTP Max Yes[1] Yes[1] VxMON OV & !CONF_OV_Vx_OTP +1 VxMON_OV_ RSTB_IMPACT VxMON_OV_ LIMP0_IMPACT VxMON UV +1 VxMON_UV_ RSTB_IMPACT VxMON_UV_ LIMP0_IMPACT First fault & FIRST_FAULT_EN_OTP Max Yes[1] Yes[1] FLT_ERR_CNT = MID VALUE No change FLT_MID_RSTB_IMPACT FLT_MID_LIMP0_IMPACT WD_ERR_CNT = WD_ERR_LIMIT +1 WD_RSTB_IMPACT WD_LIMP0_IMPACT ERRMON +1 ERRMON_FS_REACTION ERRMON_FS_REACTION RSTB request by MCU No change Yes No WD reset by MCU (WD_RSTB_REQ) No change No No LIMP0 request by MCU No change No Yes External reset (out of extended RSTB) +1 No No RSTB short to high No change No Yes LIMP0 short to high No change LIMP0_SC_RSTB_IMPACT No RSTB short 8 s Max Yes[1] Yes[1] INIT_CRC_NOK +1 No INIT_CRC_LIMP0_ IMPACT Slot 0 to Normal state 1MHz_STUCK_AT N/A Yes Yes V1_UVLP Clear at 1 Yes[1] Yes[1] WD_ERR_CNT = WD_ERR_LIMIT Clear at 1 WD_RSTB_IMPACT WD_LIMP0_IMPACT LPON state No Fault (default) Clear at 1 No No LPOFF state No Fault (default) Clear at 1 Yes by default[2] No Fail-safe state State Machine in fail-safe (default) Clear at 1 Yes by default[2] Yes by default [2] Table 44. Application related fail-safe fault list and reaction [1] By cascading effect, the fault error counter reaches its maximum value, which leads to the assertion low of RSTB and LIMP0, because the FS2400 is transitioning to Fail-safe state. [2] By default (when no fault), RSTB is asserted in LPOFF mode. In the Fail-safe state, RSTB and LIMP0 are asserted. 19.5.3 Fail-safe mode FS24 enters in Fail-safe (FS) mode when: • The fault error counter reaches its maximum value (not configurable) • VBOS UV is detected • RSTB is asserted low for 8 s (if enabled by OTP) • VxOV is detected (if configured by OTP) • VxTSD is detected (if configured by OTP) • V1UVLP is detected in LPON mode or during transition from LPON mode to Normal mode • When the first fault is detected (if configured by OTP) In Fail-safe mode, all the regulators are turned OFF, the high-power analog circuitry is disabled, the 20 MHz oscillator is disabled, the OV/UV monitoring are masked and FS_EVT bit is set to 1. The fault error counter is reset to 1 and disabled. The device exits the fail-safe state after TFS_DUR time. If FS_LPOFF_OTP bit is set to 1, the device exits FS state and goes to LPOFF. Otherwise it goes back to power-up sequence. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 72 / 151 |
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