MFS2401AVBA0ES datasheet(18/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

aaa-046839

VBAT

Vsup > Vsup_UV

Tslot

and

Tslot

Tslot +

RSTBDUR

VBOS

VDIG

Slot 0

(V1)

Slot 1

Slot 2

RSTB

TSOFT_START

Figure 11. Power-up sequence example

7.5 Debug and OTP modes

OTP emulation and programming performed by the customer is allowed during engineering development using

NXP’s latest GUI and socketed evaluation board. The customer is not allowed to perform OTP programming for

production purposes. Only NXP or a recommended third party are allowed to program the device for production

purposes.

The FS24 enters Fail-safe Debug mode when DBG pin voltage VDBG > VDBG_MODE before M4 state. It is

recommended to connect the DBG pin to the VBOS pin through a diode (VDBG = VBOS – Vd ≈ 4.3 V). The

Debug mode disables the watchdog (period configured as infinite), the RSTB 8 s timer and Fail-safe mode entry

via the fault error counter. In Debug mode, CAN transceiver is set to active mode by default. The Debug mode

status is reported by the DBG_MODE bit in M_SYS1_CFG. To exit Debug mode, write 1 in the DBG_EXIT bit in

the M_SYS1_CFG register.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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MFS2401AVBA0ES Datasheet(PDF) 18 Page - NXP Semiconductors