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MFS2401AVBA0ES Datasheet(PDF) 99 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description Report WAKE2 input state change event if not masked 0 No event on WAKE2 1 Event on WAKE2 occurred 1 WK2_I POR, or clear on write (write '1') ReportWAKE3 input state change event if not masked 0 No event on WAKE3 1 Event on WAKE3 occurred 2 WK3_I POR, or clear on write (write '1') Report HVIO1 input state change event if not masked 0 No event on HVIO1 1 Event on HVIO1 occurred 3 HVIO1_I POR, or clear on write (write '1') Report WAKE3 input state change event if not masked 0 No event on WAKE3 1 Event on WAKE3 occurred 7 WK3_I POR, or clear on write (write '1') Report LDT event 0 No event on LDT 1 Event on LDT occurred 8 LDT_I POR, or clear on write (write '1') Table 85. M_IO_TIMER_FLG register bit description 22.15 M_IO_TIMER_MSK Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 0 LDT_M Read 0 0 0 0 0 0 0 LDT_M Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write 0 0 0 0 HVIO1_M WK3_M WK2_M 0 Read 0 0 0 0 HVIO1_M WK3_M WK2_M 0 Reset 0 0 0 0 0 0 0 0 Table 86. M_IO_TIMER_MSK register bit allocation Bit Symbol Description Inhibit WAKE2 input state change interrupt 0 Interrupt is not inhibited in Normal mode 1 Interrupt is always Inhibited 1 WK2_M POR Inhibit WAKE3 input state change interrupt 0 Interrupt is not inhibited in Normal mode 1 Interrupt is always Inhibited 2 WK3_M POR Table 87. M_IO_TIMER_MSK register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 99 / 151 |
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