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MFS2401AVBA0ES Datasheet(PDF) 102 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description Inhibit SPI clock error interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 6 SPI_CLK_M POR Inhibit SPI CRC error interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 7 SPI_CRC_M POR Table 91. M_VSUP_COM_MSK register bit description...continued 22.18 M_IOWU_CFG Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 HVIO1_DGLT WK3_DGLT WK2_DGLT 0 Read 0 0 0 0 HVIO1_DGLT WK3_DGLT WK2_DGLT 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HVIO1_WUCFG WK3_WUCFG WK2_WUCFG 0 0 Read HVIO1_WUCFG WK3_WUCFG WK2_WUCFG 0 0 Reset 0 0 0 0 0 1 0 1 Table 92. M_IOWU_CFG register bit allocation Bit Symbol Description Configure WAKE2 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Reserved 2 to 3 WK2_WUCFG POR Configure WAKE3 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Reserved 4 to 5 WK3_WUCFG POR Configure HVIO1 wake-up polarity 00 Input comparator disabled in LP modes only (no consumption) 01 High-level wake-up is configured 10 Low-level wake-up is configured 11 Wake-up via mode selection is configured 6 to 7 HVIO1_WUCFG POR Table 93. M_IOWU_CFG register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 102 / 151 |
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