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MFS2401AVBA0ES Datasheet(PDF) 106 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 106 Page - NXP Semiconductors |
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106 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description Report V1 LPON undervoltage wake-up event 0 No wake-up by V1 LPON undervoltage 1 Wake-up by V1 LPON undervoltage occurred 6 V1_UVLP_WU POR, Go to LP modes (clear_all_wu_flg) Report watchdog max error failure wake-up event 0 No wake-up by max error failure 1 Wake-up by watchdog max error failure occurred 7 WD_OFL_WU POR, Go to LP modes (clear_all_wu_flg) Report RSTB assertion wake-up event 0 No wake-up by to RSTB assertion 1 Wake-up by to RSTB assertion occurred 8 EXT_RSTB_WU POR, Go to LP modes (clear_all_wu_flg) Report a fail-safe event 0 No fail-safe event 1 Fail-safe event occurred (FSM went to Fail-safe state) 9 FS_EVT POR, or clear on write (write '1') Table 101. M_WU1_FLG register bit description...continued 22.23 M_AMUX_CTRL Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 AMUX_PD_DIS 0 AMUX_EN AMUX_DIV Read 0 0 0 0 0 0 AMUX_EN AMUX_DIV Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write 0 0 0 AMUX Read 0 0 0 AMUX Reset 0 0 0 0 0 0 0 0 Table 102. M_AMUX_CTRL register bit allocation Bit Symbol Description Select AMUX input channel 00000 AGND is selected 00001 V1p6 internal voltage (VDIG) is selected 00010 V1 voltage is selected 00011 Reserved 00100 V3 voltage is selected 00101 VBOS internal voltage is selected 00110 VSUP voltage is selected (divider ratio configurable by SPI) 00111 01000 01001 01010 0 to 4 AMUX 01011 Table 103. M_AMUX_CTRL register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 106 / 151 |
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