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MFS2401AVBA0ES Datasheet(PDF) 108 Page - NXP Semiconductors

Part # MFS2401AVBA0ES
Description  Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 108 Page - NXP Semiconductors

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NXP Semiconductors
FS2400
Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
22.25 M_LDT_CFG2
Bit
15
14
13
12
11
10
9
8
Write
LDT_WUP_L
Read
LDT_WUP_L
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
LDT_WUP_L
Read
LDT_WUP_L
Reset
0
0
0
0
0
0
0
0
Table 106. M_LDT_CFG2 register bit allocation
Bit
Symbol
Description
Configure and read the 16 less significant bits of wake-up LDT timer
LDT timer value in LP mode (LSB)
0 to 15
LDT_WUP_L
POR, LDT count started
Table 107. M_LDT_CFG2 register bit description
22.26 M_LDT_CFG3
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
LDT_WUP_H
Read
LDT_WUP_H
Reset
0
0
0
0
0
0
0
0
Table 108. M_LDT_CFG3 register bit allocation
Bit
Symbol
Description
Configure and read the 8 more significant bits of LDT wake-up timer
LDT timer value in LP mode (MSB)
0 to 7
LDT_WUP_H
POR, LDT count started
Table 109. M_LDT_CFG3 register bit description
22.27 M_LDT_CTRL
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
LDT2LP
LDT_FNCT
LDT_SEL
LDT_MODE
LDT_EN
-
Table 110. M_LDT_CTRL register bit allocation
FS2400
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 23 October 2024
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