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MFS2401AVBA0ES Datasheet(PDF) 104 Page - NXP Semiconductors

Part # MFS2401AVBA0ES
Description  Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 104 Page - NXP Semiconductors

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NXP Semiconductors
FS2400
Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
Bit
Symbol
Description
Configure HVIO1 wake-up and interrupt capability
00 No wake-up and no interrupt
01 Wake=up only
10 Interrupt only
11 Wake-up and interrupt
6 to 7
HVIO1_WUEN
POR or Fail-safe state
Table 95. M_IOWU_EN register bit description...continued
22.20 M_IOWU_FLG
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
0
0
HVIO1_WU_I
0
0
WK3_WU_I
WK2_WU_I
0
Read
0
0
HVIO1_WU_I
0
0
WK3_WU_I
WK2_WU_I
0
Reset
0
0
0
0
0
0
0
0
Table 96. M_IOWU_FLG register bit allocation
Bit
Symbol
Description
Report WAKE2 wake-up event
0 No wake-up by WAKE2 (level)
1 Wake-up by WAKE2 occurred (level)
1
WK2_WU_I
POR, Go to LP modes (clear_all_wu_flg)
Report WAKE3 wake-up event
0 No wake-up by WAKE3 (level)
1 Wake-up by WAKE3 occurred (level)
2
WK3_WU_I
POR, Go to LP modes (clear_all_wu_flg)
Report HVIO1 wake-up event
0 No wake-up by HVIO1 (level)
1 Wake-up by HVIO1 occurred (level)
5
HVIO1_WU_I
POR, Go to LP modes (clear_all_wu_flg)
Table 97. M_IOWU_FLG register bit description
22.21 M_WU1_EN
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
0
0
LDT_WUEN
0
0
CAN_WUEN
Read
0
0
LDT_WUEN
0
0
CAN_WUEN
Reset
0
0
0
0
0
0
0
1
Table 98. M_WU1_EN register bit allocation
FS2400
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 23 October 2024
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