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MFS2401AVBA0ES Datasheet(PDF) 101 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 101 Page - NXP Semiconductors |
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101 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description Report SPI CRC error due to incorrect CRC calculation 0 No error 1 SPI CRC error reported 7 SPI_CRC_I POR, or clear on write (write'1) Report VBOS undervoltage event 0 No event detected 1 VBOS UV occurred 11 VBOS_UV_I POR, or clear on write (write'1) Real-time status of the switch between VBOS and V1 0 The switch is opened 1 The switch is closed 12 VBOS2V1SW_S Real-time information Table 89. M_VSUP_COM_FLG register bit description...continued 22.17 M_VSUP_COM_MSK Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write SPI_CRC_M SPI_CLK_M SPI_REQ_M 0 0 VSUPUV_ 4P7_M VSUPOV_M VSUPUV_ 4P7_M Read SPI_CRC_M SPI_CLK_M SPI_REQ_M 0 0 VSUPUV_ 4P7_M VSUPOV_M VSUPUV_ 4P7_M Reset 0 0 0 0 0 0 0 0 Table 90. M_VSUP_COM_MSK register bit allocation Bit Symbol Description Inhibit VSUPUV interrupt at 4.7 V 0 Interrupt is not inhibited 1 Interrupt is inhibited 0 VSUPUV_4P7_M POR Inhibit VSUPOV interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 1 VSUPOV_M POR Inhibit VSUPUV interrupt at 5.7 V 0 Interrupt is not inhibited 1 Interrupt is inhibited 2 VSUPUV_5P7_M POR Inhibit SPI request error interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 5 SPI_REQ_M POR Table 91. M_VSUP_COM_MSK register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 101 / 151 |
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