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MFS2401AVBA0ES Datasheet(PDF) 86 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 151 page  NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Bit Symbol Description POR, cleared when all COM flags are cleared Report an IO or LDT event IOTIMG = WK2_I or WK3_I or HVIO1_I or LDT_I 0 no event 1 event occurred 3 IOG POR, cleared when all IO and LDT flags are cleared Report a wake-up event WUG = HVIO1_WU_I or WK2_WU_I or WK3_WU_I or CAN_WU_I or LDT_WU_I or INT_TO_WU or WD_OFL_WU or V1_UVLP_WU or GO2NORMAL_WU or EXT_RSTB_WU 0 no event 1 wake-up event occurred 4 WUG POR, cleared when all WU flags are cleared Report a Physical Layer error PHYG = CAN_TSD_I or CAN_TXD_TO_I 0 no error 1 CAN error reported 5 PHYG POR, cleared when all CAN flags are cleared Report a safety related error WD_G = WD_NOK_I 0 no error 1 watchdog refresh error reported 6 WD_G POR, cleared when all WD flags are cleared Table 63. M_GEN_FLAG register bit description...continued 22.4 M_STATUS Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 0 0 Read V1TWARN_S LPON_S NORMAL_S INIT_S WK3_S WK2_S 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write 0 0 0 0 0 0 0 0 Read HVIO1_S 0 0 0 V1_MODE V1_S 0 V3_S Reset 0 0 0 0 0 0 0 0 Table 64. M_STATUS register bit allocation Bit Symbol Description Real-time status of V3 regulator 0 V3 is disabled 1 V3 is enabled 0 V3_S Real-time information Real-time status of V1 regulator 0 V1 is disabled 1 V1 is enabled 2 V1_S Real-time information Real-time status of the HVBUCK mode 3 V1_MODE 0 BUCK is in PWM mode Table 65. M_STATUS register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 86 / 151 |
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