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MFS2401AVBA0ES Datasheet(PDF) 71 Page - NXP Semiconductors |
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MFS2401AVBA0ES Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 151 page ![]() NXP Semiconductors FS2400 Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver aaa-046861 1 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK FAULT_ERR_CNT_LIMIT = 11 FAULT_ERR_CNT_LIMIT = 10 0 FLT_ERR_CNT INIT 2 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 3 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 4 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 5 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 6 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 7 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 8 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 9 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 10 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 11 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 1 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 0 FLT_ERR_CNT INIT 2 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 3 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 4 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 5 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 6 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 7 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 8 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK 12 INCR WD_RFR_CNT = WD_RFR_CNT_LIMIT + WD Refresh OK Figure 44. Fault error counter diagram with maximum value = 8 or 12 19.5.2 Fault source and reaction In normal operation when LIMP0 and RSTB are released, the fault-error counter is incremented when a fault is detected by the FS24 state machine. Table 44 lists all the faults and their impact on RSTB and LIMP0 pins according to the device configuration. The faults that are configured to not assert RSTB and LIMP0 will not increment the fault-error counter. In that case, only the flags are available for MCU diagnostic. The fault-error counter is incremented by 1, each time the RSTB and/or LIMP0 pin is asserted. In Orange, the reaction is not configurable. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback 71 / 151 |
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