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MFS2401AVBA0ES Datasheet(PDF) 148 Page - NXP Semiconductors

Part # MFS2401AVBA0ES
Description  Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2401AVBA0ES Datasheet(HTML) 148 Page - NXP Semiconductors

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NXP Semiconductors
FS2400
Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver
Tab. 102. M_AMUX_CTRL register bit allocation ..........106
Tab. 103. M_AMUX_CTRL register bit description ........106
Tab. 104. M_LDT_CFG1 register bit allocation ............. 107
Tab. 105. M_LDT_CFG1 register bit description ........... 107
Tab. 106. M_LDT_CFG2 register bit allocation ............. 108
Tab. 107. M_LDT_CFG2 register bit description ........... 108
Tab. 108. M_LDT_CFG3 register bit allocation ............. 108
Tab. 109. M_LDT_CFG3 register bit description ........... 108
Tab. 110. M_LDT_CTRL register bit allocation ............. 108
Tab. 111. M_LDT_CTRL register bit description ........... 109
Tab. 112. M_CAN register bit allocation ........................109
Tab. 113. M_CAN register bit description ......................110
Tab. 114. M_CAN register bit allocation ........................111
Tab. 115. M_CAN_MSK register bit description ............111
Tab. 116. M_MEMORY0 register bit allocation ............. 111
Tab. 117. M_MEMORY0 register bit description ........... 112
Tab. 118. M_MEMORY1 register bit allocation ............. 112
Tab. 119. M_MEMORY1 register bit description ........... 112
Tab. 120. M_HW_ID register bit allocation ....................112
Tab. 121. M_HW_ID register bit description ..................112
Tab. 122. FS_I_OVUV_CFG1 register bit allocation ..... 115
Tab. 123. FS_I_OVUV_CFG1 register bit description ... 115
Tab. 124. FS_I_OVUV_CFG2 register bit allocation ..... 115
Tab. 125. FS_I_OVUV_CFG2 register bit description ... 116
Tab. 126. FS_I_ERRMON_LIMP0_CFG register bit
allocation ....................................................... 117
Tab. 127. FS_I_ERRMON_LIMP0_CFG register bit
description ..................................................... 117
Tab. 128. FS_I_FSSM_CFG register bit allocation ........117
Tab. 129. FS_I_FSSM_CFG register bit description ..... 118
Tab. 130. FS_I_WD_CFG register bit allocation ........... 119
Tab. 131. FS_I_WD_CFG register bit description ......... 120
Tab. 132. FS_WDW_CFG register bit allocation ........... 121
Tab. 133. FS_WDW_CFG register bit description .........121
Tab. 134. FS_WD_TOKEN register bit allocation ..........122
Tab. 135. FS_WD_TOKEN register bit description ........122
Tab. 136. FS_WD_ANSWER register bit allocation ...... 122
Tab. 137. FS_WD_ANSWER register bit description .... 122
Tab. 138. FS_ LIMP0_REL register bit allocation ..........123
Tab. 139. FS_LIMP0_REL register bit description ........ 123
Tab. 140. FS_ABIST register bit allocation ................... 123
Tab. 141. FS_ABIST register bit description ................. 123
Tab. 142. FS_SAFETY_OUTPUTS register bit
allocation ....................................................... 124
Tab. 143. FS_SAFETY_OUTPUTS register bit
description ..................................................... 125
Tab. 144. FS_SAFETY_FLG register bit allocation ....... 126
Tab. 145. FS_SAFETY_FLG register bit description ..... 126
Tab. 146. FS_CRC register bit allocation ......................127
Tab. 147. FS_CRC register bit description ....................127
Tab. 148. Main OTP overview .......................................128
Tab. 149. Main OTP bits description .............................128
Tab. 150. Fail-safe OTP overview .................................133
Tab. 151. Fail-safe OTP bits description ....................... 134
Tab. 152. Revision history .............................................144
FS2400
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 23 October 2024
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