MFS2401AVBA0ES datasheet(149/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

Figures

Fig. 1.

FS24 product numbering scheme ..................... 5

Fig. 2.

Functional block diagram .................................. 7

Fig. 3.

FS2400 block diagram ...................................... 8

Fig. 4.

FS24 for UWB Simplified application

diagram ..............................................................9

Fig. 5.

FS24 for UWB and BLE Simplified

application diagram ......................................... 10

Fig. 6.

FS2400 pin configuration ................................ 11

Fig. 7.

FS2400 pin configuration legend .....................11

Fig. 8.

Detailed functional state diagram ....................15

Fig. 9.

Simplified INIT state diagram .......................... 16

Fig. 10.

Power sequencing ...........................................17

Fig. 11.

Power-up sequence example ..........................18

Fig. 12.

Debug mode ....................................................19

Fig. 13.

OTP mode time chart ......................................19

Fig. 14.

Debug pin circuitry .......................................... 19

Fig. 15.

Simplified VBOS state diagram .......................21

Fig. 16.

Application schematic, 2.2 MHz HVBUCK,

SPI interface ....................................................26

Fig. 17.

Input voltage range in LPOFF, LPON, and

NORMAL mode ...............................................29

Fig. 18.

Triangular modulation ......................................32

Fig. 19.

Pseudo-random modulation ............................ 32

Fig. 20.

Pseudo-random modulation ............................ 33

Fig. 21.

HVBUCK schematic with connection to V1_

IN .....................................................................33

Fig. 22.

HVBUCK efficiency using 2.25 MHz using

TFM252012ALMA4R7MTAA ........................... 37

Fig. 23.

HVBUCK efficiency at 2.25 MHz using

VLS3015CX-4R7M-H ...................................... 38

Fig. 24.

HVBUCK PFM efficiency .................................38

Fig. 25.

HVLDO3 application schematic .......................39

Fig. 26.

AMUX block diagram ...................................... 41

Fig. 27.

WAKEx/HIDx diagram ..................................... 43

Fig. 28.

Example of application for hardware ID

function (either using solution 1 OR 2) ............ 44

Fig. 29.

Using LIMP0 as a third HW ID pin .................. 44

Fig. 30.

HVIO1 pin ........................................................46

Fig. 31.

Example of HVIO1 pin configuration in the

slots, at power up ........................................... 47

Fig. 32.

Long duration timer block diagram ..................50

Fig. 33.

Long duration timer functions ..........................52

Fig. 34.

CAN FD transceiver internal diagram, with

external components .......................................54

Fig. 35.

CAN transceiver state machine .......................55

Fig. 36.

CAN Wake-up timing diagram .........................56

Fig. 37.

CAN timing definition according to ISO

11898-2:2016 ...................................................57

Fig. 38.

Fail-safe features block diagram ..................... 60

Fig. 39.

Window watchdog time diagram ..................... 62

Fig. 40.

Watchdog error counter configurations ............63

Fig. 41.

Watchdog refresh counter configurations ........ 64

Fig. 42.

External IC monitoring timing diagram ............ 69

Fig. 43.

Fault error counter diagram with maximum

value = 2 or 6 ................................................. 70

Fig. 44.

Fault error counter diagram with maximum

value = 8 or 12 ............................................... 71

Fig. 45.

RSTB pin implementation ............................... 73

Fig. 46.

LIMP0 pin implementation ...............................74

Fig. 47.

CRC encoder example ....................................79

Fig. 48.

SPI timing diagram ..........................................81

Fig. 49.

Top and bottom view .....................................139

Fig. 50.

Detail ............................................................. 140

Fig. 51.

Notes ............................................................. 140

Fig. 52.

Solder mask opening pattern ........................ 141

Fig. 53.

I/O pads solderable area ...............................142

Fig. 54.

Solder paste stencil .......................................143

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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MFS2401AVBA0ES Datasheet(PDF) 149 Page - NXP Semiconductors

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