AS4C64M32MD2-25BCN datasheet(11/129 Pages) ALSC

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3.2 Power-up, Initialization, and Power-Off

LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation

3.2.1 Power Ramp and Device Initialization

The following sequence shall be used to power up an LPDDR2 device.

1. Power Ramp

While applying power (after Ta), CKE shall be held at a logic low level (=< 0.2 x VDD2), all other inputs shall be

between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state

while CKE is held low.

On or before the completion of the power ramp (Tb) CKE must be held low.

DQ, DM, DQS and DQS# voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CK,

CK#, CS#, and CA input levels must be between VSSCA and VDD2 during voltage ramp to avoid latch-up.

The following conditions apply:

Ta is the point where any power supply first reaches 300 mV.

After Ta is reached, VDD1 must be greater than VDD2 - 200 mV.

After Ta is reached, VDD1 and VDD2 must be greater than VDD2 - 200 mV.

After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200 mV.

After Ta is reached, VREF must always be less than all other supply voltages.

The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV.

The above conditions apply between Ta and power-off (controlled or uncontrolled).

Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference voltages

shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high.

Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 ms.

NOTE VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply.

2. CKE and clock:

Beginning at Tb, CKE must remain low for at least tINIT1 = 100 ns, after which it may be asserted high. Clock must be

stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc). CKE, CS# and CA inputs must

observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the

subsequent falling and rising edges).

The clock period shall be within the range defined for tCKb (18 ns to 100 ns), if any Mode Register Reads are

performed.

Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are

met. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed timings (e.g. tDQSCKb) before the system is

appropriately configured.

While keeping CKE high, issue NOP commands for at least tINIT3 = 200 us. (Td).

3. Reset command:

After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally

issue a Precharge-All command (for LPDDR2-SX) to the MRW Reset command. Wait for at least tINIT4 = 1us while keeping

CKE asserted and issuing NOP commands.

4. Mode Registers Reads and Device Auto-Initialization (DAI) polling:

After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed.

Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification (see “Powerdown” ).

The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the

memory controller shall wait a minimum of tINIT5 before proceeding.

As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before

the system is appropriately configured.

After the DAI-bit (MR0, “DAI”) is set to zero “DAI complete“ by the memory device, the device is in idle state (Tf). The

state of the DAI status bit can be determined by an MRR command to MR0.

All SDRAM devices will set the DAI-bit no later than tINIT5 (10 us) after the Reset command. The memory controller

shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.

After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing

MRR commands (MR0 “Device Information” etc.).

5. ZQ Calibration:

After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). For LPDDR2

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AS4C64M32MD2-25BCN Datasheet(PDF) 11 Page - Alliance Semiconductor Corporation

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