AS4C64M32MD2-25BCN datasheet(55/129 Pages) ALSC

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x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or may

drive 0b during the MRR burst.

For LPDDR2-SX devices, MRR DQ Calibration commands may only occur in the Idle state

Table 13 — Data Calibration Pattern Description

Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3

Pattern "A"(MR32)

Pattern "B"(MR40)

Figure 4.38 — MR32 and MR40 DQ Calibration timing example: RL = 3, tMRR = 2

NOTE 1 Mode Register Read has a burst length of four.

NOTE 2 Mode Register Read operation shall not be interrupted.

NOTE 3 Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x16

devices, DQ[8] shall drive the same information as DQ[0] during the burst. For x32 devices, DQ[8], DQ[16], and DQ[24] shall drive the same

information as DQ[0] during the burst.

NOTE 4 For x8 devices, DQ[7:1] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. For x16 devices,

DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. For x32 devices, DQ[7:1],

DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b during the burst.

NOTE 5 The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period

AS4C64M32MD2-25BCN

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AS4C64M32MD2-25BCN Datasheet(PDF) 55 Page - Alliance Semiconductor Corporation