AS4C64M32MD2-25BCN datasheet(67/129 Pages) ALSC

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4.15

Input clock stop and frequency change

LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• Any Activate, Preactive, or Precharge commands have executed to completion prior to changing the frequency;

• The related timing conditions (tRCD, tRP) have been met prior to changing the frequency;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set

the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock

frequency.

LPDDR2 devices support clock stop during CKE LOW under the following conditions:

• CK is held LOW and CK# is held HIGH during clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, Preactive, or Precharge commands have executed to completion prior to stopping the clock;

• The related timing conditions (tRCD, tRP) have been met prior to stopping the clock;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must

have executed to completion, including any associated data bursts prior to changing the frequency;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the

frequency;

• CS# shall be held HIGH during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of

2tCK + tXP.

After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.

These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.

LPDDR2 devices support clock stop during CKE HIGH under the following conditions:

• CK is held LOW and CK# is held HIGH during clock stop;

• CS# shall be held HIGH during clock clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must

have executed to completion, including any associated data bursts prior to stopping the clock;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock;

• The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for

a minimum of 2tCK + tXP.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

Confidential

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Rev.1.0 July 2016

AS4C64M32MD2-25BCN Datasheet(PDF) 67 Page - Alliance Semiconductor Corporation

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