AS4C64M32MD2-25BCN datasheet(26/129 Pages) ALSC

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4.3 Read and Write access modes

4.3.1

LPDDR2-SX: Read and Write access modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS# LOW,

CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether

the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW).

The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst

read or write operation on successive clock cycles.

For LPDDR2-S4 devices, a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4

setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by

Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met.

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AS4C64M32MD2-25BCN Datasheet(PDF) 26 Page - Alliance Semiconductor Corporation