AS4C64M32MD2-25BCN datasheet(53/129 Pages) ALSC

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Transitioning data

Undefined

CK#

CA[9:0]

CMD

DQS#

DQS

RL = 3

tMRR = 2

DOUT

BL/21

DOUT

Figure 4.35 — LPDDR2: Read to MRR timing example: RL = 3, tMRR = 2

NOTE 1: The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2.

NOTE 2: The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during this period.

Figure 4.36 — LPDDR2: Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4

NOTE 1 The minimum number of clock cycles from the burst write command to the Mode Register Read

command is [WL + 1 + BL/2 + RU( tWTR/tCK)].

NOTE 2 The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during

this period.

4.11.1

Temperature Sensor

LPDDR2-SX devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to

determine an appropriate refresh rate (SDRAM), determine whether AC timing de-rating is required in the Extended

Temperature Range (SDRAM), and/or monitor the operating temperature (SDRAM). Either the temperature sensor or

the device TOPER ( See “Operating Temperature Range” ) may be used to determine whether operating temperature

requirements are being met.

LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or

power-down, the device temperature status bits shall be no older than tTSI.

When using the temperature sensor, the actual device case temperature may be higher than the TOPER specification

(See “Operating Temperature Range” ) that applies for the Standard or Extended Temperature Ranges. For example,

TCASE may be above 85o C when MR4[2:0] equals 011B.

To assure proper operation using the temperature sensor, applications should consider the following factors:

AS4C64M32MD2-25BCN

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AS4C64M32MD2-25BCN Datasheet(PDF) 53 Page - Alliance Semiconductor Corporation