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4.10

LPDDR2-SX: Self Refresh operation

The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The

LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is

defined by having CKE LOW, CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.

CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the

power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh

mode.

LPDDR2-SX devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2-

SX devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low

temperatures and higher at high temperatures. See “LPDDR2 IDD Specification Parameters and Operating Conditions”

for details.

Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.

For proper self refresh operation, power supply pins (VDD1, VDD2, and VDD2) must be at valid levels. VDDQ may be

turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA

may be at any level within minimum and maximum levels (see “Absolute Maximum DC Ratings”). However prior to

exiting Self-Refresh, VrefDQ and VrefCA must be within specified limits (see “Recommended DC Operating

Conditions”). The SDRAM initiates a minimum of one all-bank refresh command internally within tCKESR period once

it enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The

minimum time that the LPDDR2 SDRAM must remain in Self Refresh mode is tCKESR. The user may change the

external clock frequency or halt the external clock one clock after Self Refresh entry is registered; however, the clock

must be restarted and stable before the device can exit Self Refresh operation.

The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within

specified limits for a minimum of 2 tCK prior to the positive clock edge that registers CKE HIGH. Once Self Refresh

Exit is registered, a delay of at least tXSR must be satisfied before a valid command can be issued to the device to

allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSR for

proper operation except for self refresh re-entry. NOP commands must be registered on each positive clock edge

during the Self Refresh exit interval tXSR.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when

CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh

command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements outlined

in section “LPDDR2 SDRAM Refresh Requirements”, since no refresh operations are performed in power-down mode

CK#

CKE

CS#

CMD Valid

Enter

NOP

Exit

NOP

Valid

tIHCKE

tISCKE

tXSR (MIN)

tCKESR (MIN)

tIHCKE

Enter self refresh mode

Exit self refresh mode

Input clock frequency can be changed

or clock can be stopped during self refresh.

Don

＇t care

Figure 4.33 — LPDDR2-SX: Self-Refresh Operation

NOTE 1 Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a

minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency

for the particular speed grade.

NOTE 2 Device must be in the “All banks idle” state prior to entering Self Refresh mode.

NOTE 3 tXSR begins at the rising edge of the clock after CKE is driven HIGH.

NOTE 4 A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR.

4.10.1 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking

LPDDR2-S4 SDRAM has 4 or 8 banks. For LPDDR2-S4 devices, 64Mb to 512Mb LPDDR2 SDRAM has 4 banks,

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